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[KV13]
Jayanand Asok Kumar and Shobha Vasudevan.
Formal Probabilistic Timing Verification in RTL.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(5), pages 788-801, IEEE.
2013.
[Analyses timing properties of RTL designs, using the SHARPE tool and a connection to PRISM.]
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